It is known to transmit power over data lines to power remote equipment. In this way, the need for providing any external power source for the Powered Devices (PDs) can be eliminated. One form of this technology is Power Over Data Lines (PoDL) where power is transmitted over a single, twisted wire pair along with the differential data. PoDL is likely to become a popular technique, especially in automobiles.
FIG. 1 illustrates a known configuration of a PoDL system copied from US 2016/0308683. A media dependent interface (MDI) connector 160 is coupled to a twisted wire pair (not shown) carrying both differential data and a DC voltage. The coupling for both ends of the PoDL system may be identical.
A PHY 150 outputs differential data and receives differential data via the MDI connector 160, a common mode choke (CMC) 210, and AC coupling capacitors C1 and C2. PHY 150 represents the physical layer in the OSI model and is a transceiver that typically includes signal conditioning and decoding circuitry for presenting bits to the next stage. The term PHY is a term of art and is defined by various IEEE standards, depending on the particular application. The PHY is typically an integrated circuit. A digital processor (not shown) is coupled to the PHY 150 for processing the data.
If the circuit of FIG. 1 is on the PSE side, DC voltage from a power source 140 is coupled to the wires by separate inductors 142. The inductors 142 block AC and pass DC.
The wires from the MDI connector 160 are terminated by resistors R1 and R2 and capacitors C3 and C4 to minimize reflections.
FIG. 2 illustrates another prior art circuit where differential data is transmitted through a twisted wire pair 12, and common mode noise is filtered out by the CMC1 and CMC2. Since no DC voltage is conducted, AC coupling capacitors may not be needed.
A CMC is an in-line transformer with two windings in series with the twisted wire pair. As shown by the dots on the CMC windings, the windings have the same polarity, so the magnetic field generated by a differential mode signal is substantially cancelled out. Thus, the CMC presents little inductance or impedance to differential-mode currents. Common-mode currents, however, see a high impedance due to the combined inductance of the windings.
In both configurations, the CMCs ideally eliminate or greatly attenuate common mode RF noise while providing no loss for the differential or DC voltage signals. However, CMCs have constraints which impede their ideal performance. Such constraints include inter-winding capacitance, DC resistance (DCR) of the windings, and core loss. The CMCs must also present to the differential data a low insertion loss and a high return loss.
Some applications need to achieve very low bit error rates in a noisy environment, such as in a factory. Conventional CMCs alone cannot accomplish this without increasing the differential data insertion loss. The user can replace the unshielded twisted wire pair (typically an Ethernet CAT-5 cable) with a shielded cable, but this adds significant expense.
What is needed is a termination technique for differential data communications that provides a more robust technique for filtering out common mode noise.
Additionally, in some PoDL applications, the user requires to know the actual voltage at certain nodes in the system. In some applications, the voltage at the MDI connector is specified. However, this voltage cannot be measured downstream of the CMCs due to the direct current resistance (DCR) of the windings, where variations in DC current vary the losses through the windings. It is not desirable to add more connections to the MDI (possibly carrying a high PoDL current) since this may result in additional parasitic capacitance loading. It would be better to detect the MDI voltage at the PD or PSE without any connection directly at the MDI. What is needed is a technique to accurately detect the MDI voltage at the PSE or PD.